Feasibility Region Modeling of Analog Circuits for Hierarchical Circuit Design

{During hierarchical design, it becomes essential at each level of the hierarchy to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. We propose a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. In this paper we concentrate on techniques to model the feasibility region. The methodology is general and can be used for both analog and digital circuits. Macromodels are developed and veri-ed for analog blocks at diierent levels of hierarchy. An increasing percentage of IC's have analog circuit designs in them. These and other requirements stress the need for automatic synthesis tools for analog circuits. Hierarchy plays a signiicant role in the design of digital and analog circuits. A large design can be broken up into smaller sub-blocks at the diierent levels of a hierarchy. An example hierarchy for an A/D converter is shown in Figure 1. Let us consider a typical design ow for the A/D design shown in this gure. The design process is begun by rst selecting a particular design style or architecture. At each level of the hierarchy we are presented with a number of candidate design styles for each function block 1]. Each of these design styles provide the same functionality but provide diierent performance tradeoos. For example, other design styles for the A/D converter include the ash, successive approximation, and pipelined architectures. However, before we can make a selection we need to know which design styles are feasible, i.e., can be designed to meet the performance speciications. Additionally , once a number of design styles have been determined to be feasible we need to select the best candidate among these design styles, i.e., the one that provides the best performance. Obviously, one possible solution to the selection problem is to exhaustively try out all the options and then select the best candidate among them. Unfortunately, this means that we need to exhaustively design each design style to the very bottom level. This is important in ana-log circuit design because the performance of any circuit is highly dependent on the process parameters. For example , an opamp with a gain of 90dB and a unity gain band-width of 15MHz that is designable for a 1:2M process of manufacturer A may not be designable for the same feature size process of manufacturer B. …